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- HIGH PERFORMANCE AND LOW POWER HARDWARE IMPLEMENTATION FOR CRYPTOGRAPHIC HASH FUNCTIONS
- Zhang, Yunlong
- 2013-04-30, 2013-05
In this thesis, we introduce hash encryption functions which are widely used in a number of protocols as digital signature to protect privacy...
Show moreIn this thesis, we introduce hash encryption functions which are widely used in a number of protocols as digital signature to protect privacy information. Since the hash algorithm can be speeded up and be more security by physical protection, hash function hardware implementation is more desired today for evaluating its performance and processing data with dramatically increased size. Then we consider those two problems in the hash function hardware implementation: throughput and power consumption. High level of throughput is significant for the efficiency of hash algorithm. By using unfolding transformation, the throughput of hash function can be increased apparently. However, power consumption, area and critical path delay will also be increased. Pipeline and parallelism is an effective technique to decrease the critical path delay, by analyzing the construction of computing process. Another Problem is power consumption which will influence the reliability and cost of device. Clock gating is a widely used and efficiency technique for dynamic power reducing at register transfer level (RTL). There are two basic modes for single level clock gating: XOR-based clock gating and load-enable based clock gating . The former one is based on the comparing between output and input of flip-flops (FFs). Although this XOR-based clock gating technique is not used in our hash function hardware implementation, we will briefly introduce some techniques of this method which is our previous research work for dynamic power reduction by comparing some RTL low power techniques. x Next, load-enable based clock gating which works with an enable signal is introduced. According to the idle mode of some components in our simply hash encryption system, we use this load-enable based clock gating to eliminate wasted toggle rate of some signals, thus reducing dynamic power consumption. Finally, according to the source of dynamic power dissipation, reducing clock frequency is another choice. Frequency trade-off technique is proposed, which combines unrolling transformation with frequency scaling. In this technique, a scope of frequency value is given in each hash function with different number of iteration rounds for trading off low dynamic power consumption and high throughput.
M.S. in Electrical Engineering, May 2013
- Highly Robust Battery-Management System Design for Series Connected Lithium-ion Battery Packs
- Zhang, Yunlong
Because of the manufacturing variances, the individual cells in a battery pack might have different capacities and be at different levels of...
Show moreBecause of the manufacturing variances, the individual cells in a battery pack might have different capacities and be at different levels of state-of-charge (SOC). Typically, battery balancing in the battery management system (BMS) is the process to equalize the level of SOC of each battery cell in the battery pack. Without effective and appropriate battery balancing, the smallest capacity cell will limit the energy that can be delivered from or charged into the battery pack. Besides, balancing process eliminates the potential of overcharge and overdischarge which is harmful for the battery life cycles and may result in the battery pack explosion. Lithium-ion rechargeable battery cells are rather more sensitive to over-charging/discharging and over-temperature than most commonly used battery chemistries. In this thesis, we proposed the efficiency optimization of the SOC based balancing for series connected lithium-ion battery packs.There are two categories of balancing methods, passive and active. In passive balancing, energy is dissipated through resistors as heat; in active balancing, energy is transferred from the most charged cell(s) to the least charged cell(s) with equalizer(s). Since the balancing efficiency of cell-to-cell (CTC) and cell-to-pack-to-cell (CPC) active methods is higher than any other balancing technique, our optimized balancing scheme in this thesis is implemented based on these two active methods. Because we need to design and manufacture the BMS Printed circuit board (PCB), we have to figure out one optimized balancing circuit by analyzing the different initial SOC distributions and multiple balancing topologies. Not only the minimal energy dissipation of balancing process, but also the structural hazard of different balancing topologies that we need to take into account in the balancing efficiency evaluation for different balancing topologies.OrCAD capture tool from Cadence is the widely used Electronic design automation (EDA) tool to simulate the function of designed real circuit. Because it is too complicated to provided the discrepant control signals for different equalizers in OrCAD, and the simulation runtime of OrCAD will increase exponentially with the increasing number of the balancing equalizers, it is necessary to design one novel computer-aided design (CAD) tool to decrease the simulation runtime for battery packs. Finally, we obtained the optimized balancing circuit by analyzing the balancing circuit efficiency with the novel Matlab based CAD tool. The prototype of BMS PCB we designed consists of microcontroller unit (MCU), Direct current (DC) to DC converter, active balancing circuit, CAN interface and power switches which is used for overcharge and over-discharge protection.