As technology scaling continues, the performance and reliability of integrated circuits become increasingly susceptible to power supply noises... Show moreAs technology scaling continues, the performance and reliability of integrated circuits become increasingly susceptible to power supply noises, such as IR drops and Ldi/dt noises in the on-chip power grids. Reduced supply voltage levels in the grid can increase the gate delay, leading to timing violations and logic failures. In order to ensure a reliable chip design, it is critical to verify that the power grid is robust, i.e., the power supply noises are acceptable for all possible runtime situations. Hence, power grid verification has become an indispensable step in modern design flow of integrated circuits. Nowadays, it is common practice to verify power grids by simulation. Typically, an equivalent RC/RLC circuit model of the grid is extracted from the layout, and designers perform simulations to evaluate the power supply noises based on the current waveforms drawn by the circuit. As power grid simulation can only be performed after the circuit design is done, vectorless power grid verification has been introduced to enable early power grid verification with incomplete current specifications, so that the power grid design can be better tuned and optimized at early design stages, thus reducing the design time. Due to the increasing complexity of modern chips, power grid verification has become very challenging. The broad goal of this dissertation is to explore efficient algorithms for verifying large-scale on-chip power grids. Specifically, we study parallel power grid transient simulation, vectorless steady-state verification and vectorless transient verification. Parallel forward and back substitution algorithms are designed for efficient transient simulation; a set of novel algorithms are developed to incrementally improve the runtime efficiency of vectorless steady-state verification; and an efficient approach is proposed for vectorless transient verification with novel constraint setting. PH.D in Electrical Engineering, May 2013 Show less
