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HARDWARE-EFFICIENT VLSI IMPLEMENTATION FOR PARALLEL LINEAR-PHASE DIGITAL FIR FILTER
Title
HARDWARE-EFFICIENT VLSI IMPLEMENTATION FOR PARALLEL LINEAR-PHASE DIGITAL FIR FILTER
Creator
Tsao, Yu-chi
Date
2011-11, 2011-12
Description
Along with the explosive growth of multimedia applications, the number of gates required and the area consumed in very-large-scale integration...
Show moreAlong with the explosive growth of multimedia applications, the number of gates required and the area consumed in very-large-scale integration (VLSI) for digital signal processing (DSP) is getting higher and higher. Therefore, the demand for low-complexity and low-cost VLSI architectures for DSP, which occupies area as small as possible while remaining high performance, is imperatively needed. Finite impulse response (FIR) digital filter is one of the most widely used fundamental devices performed in DSP systems, ranging from wireless communications to video and image processing. Furthermore, when narrow transition band characteristics are required, the much higher order in the FIR filter is unavoidable. For instance, a 576-tap digital filter is used in video ghost canceller for broadcast television, which reduces the effect of multi-path signal echoes. On the other hand, parallel and pipelining processing are two techniques used in DSP applications, which both can be exploited to reduce the power consumption. Parallel processing applied on FIR digital filter can either increase the throughputs for high-speed processing or reduce the power consumption of the original sequential filter by lower supply voltage. Hence, there have been several architectures for parallel FIR digital filter proposed in the past. However, for symmetric convolutions, linear phase digital FIR filter, these proposed architectures are not beneficial in terms of hardware consumption. In this dissertation, new parallel FIR digital filter architectures which can save significant hardware cost by exploiting the inherent nature of symmetric convolutions, namely linear phase digital FIR filter, are presented. This dissertation is mainly divided into four chapters. In chapter one, some prerequisites as the background related to parallel finite impulse response (FIR) digital xi filter design and implementation are introduced, including conventional parallel FIR digital filter architectures, parallel FIR digital filter structures based on fast FIR algorithm (FFA), previously proposed architectures for parallel FIR filter, maximum absolute difference (MAD) quantization algorithm, canonic signed digit (CSD) representation and CSD multipliers for constant multiplications, are introduced and reviewed. In chapter two, the proposed parallel FIR digital filter structures for symmetric convolutions of even length are presented, in which the complexity and experimental results are analyzed and compared with FFA-based parallel FIR digital filter and other previously proposed structures. In chapter three, the proposed parallel FIR digital filter architectures for symmetric convolutions of odd length are presented, in which the complexity and the benefit of structures are analyzed and compared with FFA-based parallel FIR digital filter and other previously proposed structures The last chapter, chapter four, gives the summary and the conclusion of the proposed parallel linear-phase FIR digital filter.
Ph.D. in Electrical Engineering, December 2011
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