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- Leakage Power Attack-Resilient Designs of A SRAM Cell in 7nm FinFET Technology
- Chen, Kangqi
Recently, the classic metal-oxide-semiconductor field-effect-transistor (MOS- FET) has reached its limit for scaling. Another transistor...
Show moreRecently, the classic metal-oxide-semiconductor field-effect-transistor (MOS- FET) has reached its limit for scaling. Another transistor structure, FinFET, gradually has become the alternative choice for next generation of integrated circuits. Excellent features like reduced short channel effects, low threshold-voltage variability, less random dopant fluctuation, etc, offer this transistor model more stability, less leakage and faster performance. In particular, scaling trends force SRAM cells to be more vulnerable while using conventional MOSFET. The application of FinFET helps SRAM cell designs to overcome stability issues and achieve less power and faster speed. Another critical feature of an SRAM cell that needs to be considered is the correlation between data stored in cell and leakage of this cell. Side-Channel Attacks (SCA) like Leakage Power Analysis (LPA) would exploit this correlation to decrypt the secret key inside the memory. SCA has been proved to be a non-invasive but dangerous threat. Therefore, LPA would be the main focus of this thesis research.In this thesis, firstly, threshold voltage of various models are investigated using fundamental logic circuits including full-adders built with pass transistors, CLRCL and SERF. Secondly, conventional 6T SRAM cell design and single-ended 9T SRAM cell design targeting high stability and low power, are implemented and compared. Thirdly, the leakage balance method is applied to 9T cell design. Two novel solutions for LPA prevention of 9T design are proposed, implemented and compared against the original 9T design and conventional 6T design. The results confirm improved leakage balance and attack resilience while maintaining the stability and low-power features of the original 9T SRAM cell.
- Designs and Optimizations of Oblivious Data Access for Mitigating Access Pattern Leakage
- Che, Yuezhi
In today’s data-driven world, data outsourcing has grown, increasing the importance of data security and privacy. Data encryption, while...
Show moreIn today’s data-driven world, data outsourcing has grown, increasing the importance of data security and privacy. Data encryption, while providing some protection, is insufficient against side-channel attacks such as access pattern leakage. This thesis focuses on designing and optimizing efficient oblivious access methods to enhance data security and privacy. Traditional solutions, like Oblivious RAM (ORAM), often impose significant overheads, limiting their market adoption. Our research proposes novel oblivious data access schemes tailored to specific applications, systems, and contexts. This approach enables us to identify critical vulnerabilities and performance bottlenecks, and balance performance, security, and other relevant parameters. In this thesis, I present four published works in Chapters 3 to 6, demonstrating the effectiveness of my proposed methods: (1) optimizing Ring ORAM for multi-channel memory systems, (2) introducing a multi-range supported ORAM for locality-aware applications, (3) proposing an oblivious data access solution for NVM hybrid memory systems, and (4) developing an oblivious access method for deep neural networks (DNNs), ensuring privacy without sacrificing performance. These contributions address unique challenges across application domains, enhancing data security and privacy in contemporary computing systems. This thesis provides a comprehensive investigation of targeted oblivious access methods, highlighting the benefits of the proposed designs, and contributing to more effective solutions for access pattern leakage mitigation, ultimately improving data security and privacy in contemporary computing systems.