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CMOS POLAR DIGITAL POWER AMPLIFIER FOR HIGH DATA RATE WIRELESS COMMUNICATIONS
Title
CMOS POLAR DIGITAL POWER AMPLIFIER FOR HIGH DATA RATE WIRELESS COMMUNICATIONS
Creator
Zhu, Qiuyao
Date
2016, 2016-12
Description
Power amplifier (PA) is the most important circuit block in an RF transmitter. It typically consumes more than 80% of the power taken by the...
Show morePower amplifier (PA) is the most important circuit block in an RF transmitter. It typically consumes more than 80% of the power taken by the entire transmitter. Therefore, a highly efficient PA is the key to a successful RF front-end system. The polar transmitter architecture is studied herein in order to take advantage of the highly efficient switching-mode PA. However, due to the large expanded bandwidth from the nonlinear IQ to polar conversion and the sensitive amplitude/phase delay impairment, hardly any reported polar design is able to transmit high data rate wireless communication signals. In this work, an extensive research on the digital polar transmitter system for high data rate signals is presented. An integrated CMOS digital power am- plifier (DPA) design is demonstrated afterwards. This DPA consists of 9-bit fully thermometer-coded uniform cells to achieve high linearity for wide bandwidth OFDM signals. By analyzing the amplitude and phase paths impairment, which will cause both in-band and out-of-band distortions, a 960 MHz digital delay tuner is designed for precise amplitude and phase alignment. Furthermore, two digital pre-distortion algorithms for DPA are implemented and compared. Importantly, an on-chip DC- DC converter is included for direct battery connection and power control. A boosted cascode gate bias improves PA efficiency at the low power region. The proposed design is fabricated using a 55 nm RF CMOS technology. The DPA with several peripheral blocks occupies only 0.63 mm2 active silicon area. This DPA including the digital AM filtering achieves a peak output power of +21.9 dBm with 41% efficiency. It achieves EVM of 2.9% with 20 MHz IEEE 802.11ac compliance of 256-QAM OFDM signals, and also achieves EVM of 4.5% (CC0) / 4.8% (CC1) with 2 x 20 MHz 3GPP LTE-Advanced carrier aggregation compliance of 64-QAM OFDM signals. This highly linear DPA has demonstrated high flexibility, high efficiency, and small area. To the author's knowledge, this is the first reported DPA that meets either the linearity requirements of 256-QAM OFDM signals or the signal bandwidth of 40 MHz, paving the path for wideband high data rate wireless applications using digital polar architecture. At the same time, aiming at a higher average efficiency, a two-level class- G supply modulator is investigated to dynamically switch the DPA VDD. It has successfully demonstrated an average efficiency of 34.6% for this class-G modulated DPA in a complete circuit simulation using the IEEE 802.11b signal.
Ph.D. in Electrical Engineering, December 2016
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