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Title

DESIGN AND ANALYSIS OF DATAPATH CIRCUITS USING MULTI-GATE TRANSISTORS

Creator

Garcia Martin, Martin

Date

2015, 2015-07

Description

Multi-Gate Field-E ect Transistors are transistors with more than one gate that allows continuation of Moore's Law and performance increases...
Show moreMulti-Gate Field-E ect Transistors are transistors with more than one gate that allows continuation of Moore's Law and performance increases for CMOS tran- sistors. Introduction of multi-gate devices has been a turning point for the semi- conductor industry in facilitating transition from planar to 3D structures. Intel rst introduced commercial products using 3D structures (called Tri-Gate transistors) in late 2011 with Ivy Bridge CPUs using 22nm processes. Signi cant performance gains have been reported; i.e., 37% performance increase at low voltage and 50% power reduction. Multi-gate transistors based on 3D structures can vary greatly in their con guration and architectures leading to ambiguity in their design. It is necessary to investigate the performance of datapath circuits when multi-gate and independent- gate devices replace the conventional planar transistors. Therefore, key objective of this work has been to analyze these transistors' performance and to design new dat- apath circuits to leverage the inherent qualities of multi-gate transistor structures. Multiple-gate devices can be modeled using the BSIM-CMG (Common Multi- Gate) and BSIM-IMG (Independent Multi-Gate) compact models from University of Berkeley Device Group. In this research, both device types have been characterized for a variety of parameters to study their basic properties, functionality and to build a foundation for improved circuit designs. In particular, BSIM-CMG devices have been compared with CMOS planar technology demonstrating signi cant advantages in all design metrics, meanwhile the BSIM-IMG have been used to design new gates and improve datapath designs. In the rst part of this study, essential logic gates, i.e. Inverter, NAND and NOR, have been implemented using BSIM-CMG devices. After being analyzed and compared with the CMOS technology, a 32% reduction on dynamic power consump- tion and 82% reduction for the leakage current has been obtained. For a compre-hensive look on full adder designs, several novel adder architectures have been im- plemented including ultra low power and minimum number of transistor (10T) de- signs. The analysis of these implementations shows 54% dynamic power reduction, 98% static current reduction and 26% delay reduction. These results lead to a 68% improvement on the Power-Delay product comparing with the 32nm CMOS planar technology. In order to investigate dynamic logic circuits with multi-gate transistors, two recent dynamic circuit techniques have been implemented with novel enhancements to reduce the leakage current. Data Driven Dynamic Logic (D3L) and Split-Path Data Driven Dynamic Logic (SPD3L) have been used to analyze the dynamic logic circuits resulting in 11% reduced dynamic power, 52% reduced leakage current and 33% reduced delay. Second part of this study deals with the independent gate devices. Using the BSIM-IMG model, new XOR/XNOR logic gate designs are introduced for im- plementing novel low-power adders. With these new adder architectures, the average improvement on Dynamic power is an 8% and the designs are 6% faster. Furthermore, a new design technique is proposed combining the possible modes (Short Gate-SG, Low-Power-LP, Independent Gate-IG) that the BSIM-IMG provides. Using this novel mixed design, the Power-Delay product is improved on average 7.2% and 54%, com- pared to the Short-Gate (SG) and Low-Power (LP) modes, respectively. The properties of the BSIM-IMG logic have been applied to improve the Dy- namic logic designs as well. The Domino and SPD3L design techniques have been implemented and enhancements such as merging the pull-up transistors have been proposed for sleep and power-gating techniques. With these enhancements, the Dy- namic power is reduced 13% in average and the designs are 18% faster. The trade-o is an increase on leakage current of 8%. Another major contribution of the work has been the development of shell script les for generating a custom toolbox for datapath designs with multi-gate and independent-gate transistors.
Ph.D. in Electrical and Computer Engineering, July 2015
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