Search results

(1 - 2 of 2)

Title

POWER OPTIMIZATION IN DEEP SUBMICRON VLSI CIRCUITS: FROM SYSTEM LEVEL TO CIRCUIT LEVEL

Creator

Tong, Qiang

Date

2017, 2017-07

Description

As VLSI technology advances to deep sub-micron regime, power consumption has become a critical concern in VLSI circuits. Therefore, power...
Show moreAs VLSI technology advances to deep sub-micron regime, power consumption has become a critical concern in VLSI circuits. Therefore, power optimization becomes mandatory in VLSI design nowadays. To reduce the power consumption, many techniques have been proposed at various levels of VLSI circuits design: system level, register-transfer level(RTL), and circuit/transistor level. This dissertation starts with a review of system level power optimization techniques. Experiments on a computer architecture simulation system have been conducted to compare the impact of different programming styles at system level on power consumption. The results could be used as an intuitive guidance for programmers with intention for implementing power-aware system. The second topic in this dissertation is a clustering based clock gating technique, targeting power reduction at RT-Level. Clock gating is an effective and popular method to reduce dynamic power in VLSI circuits, it can be applied at both RT-level and gate level. The basic idea of clock gating is to disable the clock of one or more sequential logics (majorly flip-flops) when the input data of the logic cells do not change. In this dissertation, a clustering based clock gating technique is proposed, the technique exploits activity information of each flip-flop, and clusters them into groups according to their activity correlations. As the leakage power has become a major concern in VLSI design, the proposed As the leakage power has become a major concern in VLSI design, the proposed clustering method is extended down to gate level and a clustering based hybrid clock gating and power gating technique is proposed. The technique can reduce both the dynamic power and leakage power in VLSI circuits. As process technology scaling down to deep submicron regime, bulk CMOS technology has encountered many challenges due to short channel effect (SCE), which degrades the reliability and feasibility of MOSFET devices. New technologies such as FinFET and carbon nanotube FET (CNFET) are two promising substitute solutions in the following decade to address SCE issue. Part of this dissertation presents circuit design using these new process technologies for low power VLSI circuits. More specifically, two SRAM cell designs using FinFET and CNFET devices are proposed. The new designs can improve performance while reduce power consumption.
Ph.D. in Electrical Engineering, July 2017
Show less

Title

NOVEL 8-T CNFET SRAM CELL DESIGN FOR FUTURE ULTRA-LOW POWER MICROELECTRONICS

Creator

Kim, Youngbae

Date

2016, 2016-05

Description

In deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to...
Show moreIn deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to build the cache in System-on-Chip (SOC). In this paper, a low power 8-T SRAM cell, based on carbon nanotube field effect transistor (CNFET), is proposed to circumvent the leakage power issue. Experiment datas show that the proposed SRAM cell can save 97.94% static power consumption compared to existing 6T CNFET SRAM cell. In case of writing, the proposed SRAM cell consumes 39.27% less power than the traditional SRAM cell for writing 0 and 58.79% less for writing 1. Also, because of the adoption of a colaborated voltage sense amplifier and independent read component, our 8T SRAM shows much improved delay performance, the delay is observed to reduce by approximate 30% in write operation and approximate 90% in read operation.
M.S. in Electrical Engineering, May 2016
Show less