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- Title
- COOPERATIVE BATCH SCHEDULING FOR HPC SYSTEMS
- Creator
- Yang, Xu
- Date
- 2017, 2017-05
- Description
-
The batch scheduler is an important system software serving as the interface between users and HPC systems. Users submit their jobs via batch...
Show moreThe batch scheduler is an important system software serving as the interface between users and HPC systems. Users submit their jobs via batch scheduling portal and the batch scheduler makes scheduling decision for each job based on its request for system resources and system availability. Jobs submitted to HPC systems are usually parallel applications and their lifecycle consists of multiple running phases, such as computation, communication and input/output data. Thus, the running of such parallel applications could involve various system resources, such as power, network bandwidth, I/O bandwidth, storage, etc. And most of these system resources are shared among concurrently running jobs. However, Today's batch schedulers do not take the contention and interference between jobs over these resources into consideration for making scheduling decisions, which has been identified as one of the major culprits for both the system and application performance variability. In this work, we propose a cooperative batch scheduling framework for HPC systems. The motivation of our work is to take important factors about jobs and the system, such as job power, job communication characteristics and network topology, for making orchestrated scheduling decisions to reduce the contention between concurrently running jobs and to alleviate the performance variability. Our contributions are the design and implementation of several coordinated scheduling models and algorithms for addressing some chronic issues in HPC systems. The proposed models and algorithms in this work have been evaluated by the means of simulation using workload traces and application communication traces collected from production HPC systems. Preliminary experimental results show that our models and algorithms can effectively improve the application and the system overall performance, HPC facilities' operation cost, and alleviate the performance variability caused by job interference.
Ph.D. in Computer Science, May 2017
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- Title
- CHARACTERIZING GPS PHASE LOCK LOOP PERFORMANCE IN WIDEBAND INTERFERENCE USING THE DISCRIMINATOR OUTPUT DISTRIBUTION
- Creator
- Stevanovic, Stefan
- Date
- 2018, 2018-05
- Description
-
The use of the Global Positioning System (GPS) has accelerated in recent years. In its inception, GPS was used exclusively by the military for...
Show moreThe use of the Global Positioning System (GPS) has accelerated in recent years. In its inception, GPS was used exclusively by the military for navigation. Today, with the emergence of extremely capable electronics and microprocessors, GPS has been integrated into many aspects of life. It is currently widely used by both the military and various civilian industries for applications that require navigation as well as precise timing. Some applications of GPS include ground vehicle and aircraft navigation, banking, power transmission, and agriculture. As a result, disruptions in GPS availability have the potential to disrupt many services and industries around the globe, and even threaten the safety of life. Reliable operation can be interrupted by radio frequency interference (RFI), which can come from natural and manufactured sources. This work describes new techniques to evaluate the performance of GPS receivers that may be subjected to RFI events. The example application motivating this work is Ground Based Augmentation System (GBAS) reference station receivers subjected to broadband interference, for example, from nearby use of personal privacy devices (PPDs). PPDs most commonly emit broadband interference, and GBAS ground based reference receivers have expe- rienced tracking discontinuities as a result [Pul12]. These events can cause navigation service interruptions to aircraft on nal approach. To ensure continuity of the nav- igation service, GBAS reference stations must be able to track GPS signals in the presence of wideband interference. The objective of this work is to develop the PLL analysis tools required to design PLLs capable of tracking through RFI events, while reducing the need for time-consuming simulations and experimental validation. Instead, simulation and experimental validation can be reserved for PLL designs which are much more likely to be successful. The techniques described in this work are valid for any GPS application in which the receiver cannot tolerate cycle slips in the phase-lock loop (PLL). The methodology is directly applicable to ground-based reference receivers for differential GPS systems, as well as other ground-based receivers that require high continuity of service. It is also relevant to moving receivers, if the additional dynamic stresses on the PLL are also taken into account. The PLL discriminator output (DO) distribution is used to characterize GPS PLL tracking performance, in contrast to the phase jitter metric widely used in prior work and literature. Both the DO variance and the bias on the mean of the DO distribution are shown to be superior to the jitter metric in predicting phase-lock. And, it is shown that the bias in the DO mean is the most effective measure of cycle slip probability. Studying the discriminator output distribution also provides a means of comparing different techniques to extend PLL averaging time beyond the length of a navigation data bit, without time-consuming direct simulation and experimental validation. Experimental results are presented to validate the theoretical analysis and simulations. The observed tracking results are consistent with the theoretically predicted system performance. The DO bias is superior to the variance metric in its ability to predict loss of phase-lock.
Ph.D. in Mechanical and Aerospace Engineering, May 2018
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