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(1 - 4 of 4)
- Title
- POWER OPTIMIZATION IN DEEP SUBMICRON VLSI CIRCUITS: FROM SYSTEM LEVEL TO CIRCUIT LEVEL
- Creator
- Tong, Qiang
- Date
- 2017, 2017-07
- Description
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As VLSI technology advances to deep sub-micron regime, power consumption has become a critical concern in VLSI circuits. Therefore, power...
Show moreAs VLSI technology advances to deep sub-micron regime, power consumption has become a critical concern in VLSI circuits. Therefore, power optimization becomes mandatory in VLSI design nowadays. To reduce the power consumption, many techniques have been proposed at various levels of VLSI circuits design: system level, register-transfer level(RTL), and circuit/transistor level. This dissertation starts with a review of system level power optimization techniques. Experiments on a computer architecture simulation system have been conducted to compare the impact of different programming styles at system level on power consumption. The results could be used as an intuitive guidance for programmers with intention for implementing power-aware system. The second topic in this dissertation is a clustering based clock gating technique, targeting power reduction at RT-Level. Clock gating is an effective and popular method to reduce dynamic power in VLSI circuits, it can be applied at both RT-level and gate level. The basic idea of clock gating is to disable the clock of one or more sequential logics (majorly flip-flops) when the input data of the logic cells do not change. In this dissertation, a clustering based clock gating technique is proposed, the technique exploits activity information of each flip-flop, and clusters them into groups according to their activity correlations. As the leakage power has become a major concern in VLSI design, the proposed As the leakage power has become a major concern in VLSI design, the proposed clustering method is extended down to gate level and a clustering based hybrid clock gating and power gating technique is proposed. The technique can reduce both the dynamic power and leakage power in VLSI circuits. As process technology scaling down to deep submicron regime, bulk CMOS technology has encountered many challenges due to short channel effect (SCE), which degrades the reliability and feasibility of MOSFET devices. New technologies such as FinFET and carbon nanotube FET (CNFET) are two promising substitute solutions in the following decade to address SCE issue. Part of this dissertation presents circuit design using these new process technologies for low power VLSI circuits. More specifically, two SRAM cell designs using FinFET and CNFET devices are proposed. The new designs can improve performance while reduce power consumption.
Ph.D. in Electrical Engineering, July 2017
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- Title
- NOVEL 8-T CNFET SRAM CELL DESIGN FOR FUTURE ULTRA-LOW POWER MICROELECTRONICS
- Creator
- Kim, Youngbae
- Date
- 2016, 2016-05
- Description
-
In deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to...
Show moreIn deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to build the cache in System-on-Chip (SOC). In this paper, a low power 8-T SRAM cell, based on carbon nanotube field effect transistor (CNFET), is proposed to circumvent the leakage power issue. Experiment datas show that the proposed SRAM cell can save 97.94% static power consumption compared to existing 6T CNFET SRAM cell. In case of writing, the proposed SRAM cell consumes 39.27% less power than the traditional SRAM cell for writing 0 and 58.79% less for writing 1. Also, because of the adoption of a colaborated voltage sense amplifier and independent read component, our 8T SRAM shows much improved delay performance, the delay is observed to reduce by approximate 30% in write operation and approximate 90% in read operation.
M.S. in Electrical Engineering, May 2016
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- Title
- Leakage Power Attack-Resilient Designs of A SRAM Cell in 7nm FinFET Technology
- Creator
- Chen, Kangqi
- Date
- 2019
- Description
-
Recently, the classic metal-oxide-semiconductor field-effect-transistor (MOS- FET) has reached its limit for scaling. Another transistor...
Show moreRecently, the classic metal-oxide-semiconductor field-effect-transistor (MOS- FET) has reached its limit for scaling. Another transistor structure, FinFET, gradually has become the alternative choice for next generation of integrated circuits. Excellent features like reduced short channel effects, low threshold-voltage variability, less random dopant fluctuation, etc, offer this transistor model more stability, less leakage and faster performance. In particular, scaling trends force SRAM cells to be more vulnerable while using conventional MOSFET. The application of FinFET helps SRAM cell designs to overcome stability issues and achieve less power and faster speed. Another critical feature of an SRAM cell that needs to be considered is the correlation between data stored in cell and leakage of this cell. Side-Channel Attacks (SCA) like Leakage Power Analysis (LPA) would exploit this correlation to decrypt the secret key inside the memory. SCA has been proved to be a non-invasive but dangerous threat. Therefore, LPA would be the main focus of this thesis research.In this thesis, firstly, threshold voltage of various models are investigated using fundamental logic circuits including full-adders built with pass transistors, CLRCL and SERF. Secondly, conventional 6T SRAM cell design and single-ended 9T SRAM cell design targeting high stability and low power, are implemented and compared. Thirdly, the leakage balance method is applied to 9T cell design. Two novel solutions for LPA prevention of 9T design are proposed, implemented and compared against the original 9T design and conventional 6T design. The results confirm improved leakage balance and attack resilience while maintaining the stability and low-power features of the original 9T SRAM cell.
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- Title
- A Novel CNFET SRAM-Based Computing-In-Memory Design and Low Power Techniques for AI Accelerator
- Creator
- Kim, Young Bae
- Date
- 2023
- Description
-
Power consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI...
Show morePower consumption and data processing speed of integrated circuits (ICs) is an increasing concern in many emerging Artificial Intelligence (AI) applications, such as autonomous vehicles and Internet of Things (IoT). In addition, according to the 2020 International Technology Road map for Semiconductors (ITRS), the high power consumption trend of AI chips far exceeds the power requirements. As a result, power optimization techniques are highly regarded in nowadays AI chip designs. There are various low-power methodologies from the system level to the layout level, and we are focusing on transistor level and register transfer level (RTL) through this thesis. In this thesis, we propose a novel ultra-low power voltage-based computing-in- memory (CIM) design with a new SRAM bit cell structure for AI Accelerator. The basic working principle of CIM (Computing-in-memory) is to use the existing internal embedded memory array (e.g. SRAM) instead of external memory, and it reduces unnecessary access to external memory by calculating with internal embedded mem- ory. Since the proposed our SRAM bit cell uses a single bitline for CIM calculation with decoupled read and write operations, it supports much higher energy eciency. In addition, to separate read and write operations, the stack structure of the read unit minimizes leakage power consumption. Moreover, the proposed bit cell structure provides better read and write stability due to the isolated read path, write path and greater pull-up ratio. Compared to the state-of-the-art SRAM-CIM, our proposed SRAM-CIM does not require extra transistors for CIM vector-matrix multiplication. We implemented a 16k (128⇥128) bit cell array for the computation of 128x neurons, and used 64x binary inputs (0 or 1) and 64⇥128 binary weights (-1 or +1) values for the binary neural networks (BNNs). Each row of the bit cell array corresponding to a single neuron consists of a total of 128 cells, 64x cells for dot-product and 64x replicas cells for ADC reference. And 64x replicas cells consist of 32x cells for ADC reference and 32x cells for o↵set calibration. We used a row-by-row ADC for the quantized outputs of each neuron, which supports 1-7 bits of output for each neuron. The ADC uses the sweeping method using 32x duplicate bit cells, and the sweep cycle is set to 2N1 +1, where N is the number of output bits. The simulation is performed at room temperature (27C) using 32nm CNFET and 20nm FinFET technology via Synopsys Hspice, and all transistors in bitcells use the minimum size considering the area, power, and speed. The proposed SRAM-CIM has reduced power consumption for vector-matrix multiplication by 99.96% compared to the existing state-of-the-art SRAM-CIM. Moreover, because of the separated reading unit from an internal node of latch, there is no feedback from the read access circuit, which makes it read static noise margin (SNM) free. Furthermore, for the low power AI accelerator design, we propose a new AI accelerator design method that applies low power techniques such as bus specific clock gating (BSCG) and local explicit clock gating (LECG) at the register-transfer- level (RT-level). And evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45nm technology for ASIC, respectively. It measures dynamic power using a commercial EDA tool, and chooses only a subset of FFs to be gated selectively based on their switching activities. We achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the AI system.
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