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POWER GRID VERIFICATION ON CLOUD
Title
POWER GRID VERIFICATION ON CLOUD
Creator
Gupte, Naval
Date
2016, 2016-05
Description
Reliability and performance of modern ICs is becoming increasingly susceptible to supply voltage variations. Increased demand for low voltage...
Show moreReliability and performance of modern ICs is becoming increasingly susceptible to supply voltage variations. Increased demand for low voltage integrated circuits has made power grid analysis extremely critical and indispensable in modern design flows. Efficient validation of on-chip power distribution network is computationally demanding because of increasing grid sizes. Power grid simulation is critical for analysis and verification of power supply noises for robust and reliable IC designs. Computational demands to simulate power grids for ICs with increasing complexity is never-ending. Cloud computing platforms can be leveraged to mitigate costs associated with making these resources available. However, since simulation data usually contains sensitive design information, simulating on third-party platforms lead to major security concerns. In this study, we propose a framework for secure power grid simulation on Cloud. A transformation algorithm to hide current excitations is presented, while still allowing a majority of computations to be completed on Cloud. We employ multiple compression strategies to significantly reduce communication and storage overheads. Experiments show that our framework can achieve similar turn-around time as an insecure simulator on Cloud, while securing current excitations and output voltage vectors with reasonable communication and computational overheads. Vectorless technique to grid verification estimates worst-case voltage noises without detailed enumeration of load current excitations. We study voltage noise assessment in RLC models of VDD and GND networks in integrated power grids. Abstract grid model is utilized to abbreviate runtime, while transient constraints capture transitory circuit behaviour. Heuristics are employed to extract constraints that restrict power consumption profiles to realistic scenarios. Multiple linear programming problems are formulated to evaluate bounds on voltage overshoots and undershoots. We propose ways to mitigate storage and computational requirements on processing resources, enabling users to deploy computations on economical Cloud Computing platforms. Recommended solution is parallelizable, thereby reducing the overall verification time. Data compression is applied to fully exploit the compute capabilities of contemporary processors for higher throughputs. Experimental results suggest that the proposed technique is practical and scalable for industrial grids.
Ph.D. in Electrical Engineering, May 2016
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AUTOMATION OF ULTRASONIC FLAW DETECTION APPLICATIONS USING DEEP LEARNING ALGORITHMS
Title
AUTOMATION OF ULTRASONIC FLAW DETECTION APPLICATIONS USING DEEP LEARNING ALGORITHMS
Creator
Virupakshappa, Kushal
Date
2021
Description
The Industrial Revolution-4.0 promises to integrate multiple technologies including but not limited to automation, cloud computing, robotics,...
Show moreThe Industrial Revolution-4.0 promises to integrate multiple technologies including but not limited to automation, cloud computing, robotics, and Artificial Intelligence. The non-Destructive Testing (NDT) industry has been shifting towards automation as well. For ultrasound-based NDT, these technological advancements facilitate smart systems hosting complex signal processing algorithms. Therefore, this thesis introduces the effective use of AI algorithms in challenging NDT scenarios. The first objective is to investigate and evaluate the performance of both supervised and unsupervised machine learning algorithms and optimize them for ultrasonic flaw detection utilizing Amplitude-scan (A-scan) data. Several inferences and optimization algorithms have been evaluated. It has been observed that proper choice of features for specific inference algorithms leads to accurate flaw detection. The second objective of this study is the hardware realization of the ultrasonic flaw detection algorithms on embedded systems. Support Vector Machine algorithm has been implemented on a Tegra K1 GPU platform and Supervised Machine Learning algorithms have been implemented on a Zynq FPGA for a comparative study. The third main objective is to introduce new deep learning architectures for more complex flaw detection applications including classification of flaw types and robust detection of multiple flaws in B-scan data. The proposed Deep Learning pipeline combines a novel grid-based localization architecture with meta-learning. This provides a generalized flaw detection solution wherein additional flaw types can be used for inference without retraining or changing the deep learning architecture. Results show that the proposed algorithm performs well in more complex scenarios with high clutter noise and the results are comparable with traditional CNN and achieve the goal of generality and robustness.
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