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SOFT ERROR TOLERANT LATCH CIRCUIT DESIGN FOR DEEPLY SCALED CMOS TECHNOLOGY
Title
SOFT ERROR TOLERANT LATCH CIRCUIT DESIGN FOR DEEPLY SCALED CMOS TECHNOLOGY
Creator
Nan, Haiqing
Date
2012-01-25, 2012-05
Description
As CMOS technology keeps scaling down, circuit designers face variety of challenges. Due to the scaling of supply voltage and node capacitance...
Show moreAs CMOS technology keeps scaling down, circuit designers face variety of challenges. Due to the scaling of supply voltage and node capacitance, digital circuits are more aware of noise and variations, which cause reliability issues such as soft error. Traditionally the soft error aware VLSI design is limited to applications which require high reliability and operated in high radiation environment such as avionics applications, medical equipments, space industry and military applications. However, with CMOS technology scales down to nanometer region, the VLSI circuits can also be affected by soft errors at ground level which features low radiation energy. In this thesis, totally 5 soft error tolerant latch designs are proposed including HLR-1, HLR-2, HLR-CG1, HLR-CG2, and HLR-CG3. All the proposed designs protect internal nodes as well as output node for soft error regardless the radiation energy. The proposed HLR-1 and HLR-2 latch circuits tolerate soft error for non-CG systems. Since the proposed HLR-1 and HLR-2 designs take advantages of floating node to tolerate soft error, these two designs cannot be applied with clock gating techniques and the minimum clock frequency of these two designs should be greater than 16MHz in order to maintain correct logic at the floating node. The power consumption and circuit delay between the proposed HLR-1 and HLR-2 designs are very close. The proposed HLR-1 design achieves a small amount of benefits in terms of power and delay compared with the proposed HLR-2 design. But the proposed HLR-2 circuit reduces area 3.5% compared to the proposed HLR-1 circuit. The proposed HLR-CG1, HLR-CG2 and HLR-CG3 latch designs fully tolerate soft error regardless of radiation energy for both CG and non-CG systems. Due to the auto correction mechanism embedded in the proposed HLR-CG1, HLR-CG2 and HLRCG3 designs, any soft error at any location will be automatically corrected without generating any floating nodes. The proposed HLR-CG3 features the smallest power consumption and delay but it has the largest area overhead compared to HLR-CG1 and HLR-CG2 circuits. The proposed HLR-CG1 design features the smallest area compared with HLRCG2 and HLR-CG3 designs. The design cost of HLR-CG2 design is between the proposed HLR-CG1 and HLR-CG3 designs. All the proposed designs achieve faster speed and smaller PDP compared to previous hardening techniques. Compared to the proposed HLR-1 design, previous designs increases power 3.77% on average, delay 272.74% on average, PDP 300.29% on average and decreases area 7.09% on average. Compared to the proposed HLR-2 design, previous designs increases power 3.77% on average, delay 272.40% on average, PDP 299.89% on average and decreases area 3.93% on average. Compared to the proposed HLR-CG1 design, previous designs increases area 19.65% on average, delay 213.14% on average, PDP 203.78% on average and decreases power 5.82% on average. Compared to the proposed HLR-CG2 design, previous designs increase area 6.49% on average, delay 193.28% on average, PDP 223.45% on average and power 6.51% on average. Compared to the proposed HLR-CG3 design, previous designs increases delay 272.18% on average, PDP 314.38% on average, power 8.01% on average and area 2.93% on average.
Ph.D. in Electrical and Computer Engineering, May 2012
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