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Title

Polymorphic Network-on-Chip Datapath Architecture for Reconfigurable Computing Machines

Creator

Weber, Joshua

Date

2012-04-18, 2012-05

Description

Polymorphic processors have considerable advantages in performance over existing reconfigurable designs. Polymorphic processors combine the...
Show morePolymorphic processors have considerable advantages in performance over existing reconfigurable designs. Polymorphic processors combine the flexibility and ease of a general purpose processor with the performance optimizations made possible through reconfigurable arrays. Polymorphic processors provide all the ease of programming from a traditional general purpose processor while incorporating the significant performance gains that can be realized using reconfigurable arrays. Polymorphic processors can be categorized by the level of integration between the general purpose processor and the reconfigurable array. At coarse levels of integration, the processor and reconfigurable array execute independently and exchange data utilizing bus structures. These systems perform robustly for high level datadriven optimizations, allowing large segments of processing to be quickly performed on fast reconfigurable resources. However, the overhead of data transfer between the processor and array limits the benefit to fine grained optimizations. Other architectures attempt a tight coupling of reconfigurable arrays, placing them within the processor as reconfigurable coprocessors and functional units. This technique allows fine grained optimizations of small scale, highly repeated computations, but finds it difficult to replicate the gains made in large coarse grained optimizations. To achieve an even more tightly coupled design than any prior work, the fundamental architecture of the processor is changed. The datapath of the processor is eliminated and replaced with a network-on-chip communications framework. This framework connects a system of reconfigurable arrays. Some of these reconfigurable blocks are tasked with execution of standard, general purpose processor computations, emulating the standard pipeline stages of a SPARC processor. Additional reconfigurable blocks are available to the end-user to incorporate custom application specific optimizations. This new polymorphic NoC datapath (PolyNoC) processor is able to provide a more tightly integrated architecture with significant performance advantages. The PolyNoC processor is able to incorporate both fine and coarse grained optimizations, producing a polymorphic processor able to provide performance improvements for a wide range of target applications. This thesis presents the architectural design of the PolyNoC processor. The unique design constraints resulting from the use of the NoC as a datapath will be fully explored. The impact of these constraints will be incorporated into the design of a suitable NoC for the PolyNoC processor. A cycle-accurate simulator of the PolyNoC processor has been constructed. This simulator is used to examine the performance of the PolyNoC processor when executing unmodified, industry standard benchmark programs. To demonstrate the advantages of application specific extensions to the processor, accelerators are added for each benchmark. The performance of the Poly- NoC processor is promising.
Ph.D. Computer Science, May 2012
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