With the development of CMOS technology, the performance including power dissipation and operation speed is highly concerned for SRAM design.... Show moreWith the development of CMOS technology, the performance including power dissipation and operation speed is highly concerned for SRAM design. Desirable low power consumption while operating fast is the goal of design and improvement. However, the tradeoff between performance and speed is one of the most challenging obstacles that engineers are facing. Along with continuously scaling in the process technology, the concern for stability of Static Random Access Memories (SRAMs) is increasing in the design and test. Maintaining an acceptable Static Noise Margin (SNM) as well as scaling the minimum feature sizes and supply voltages of the Systems-on-a-Chip (SoC) becomes more and more challenging. Subthreshold leakage, dynamic power consumption and delay are major issues for circuits design, especially for SRAM design. Subthreshold leakage and dynamic power consumption can be decreased while supply voltage is scaled down. However, this may dramatically increase the circuit delay (Lindert, 1999) (Wang, 2004) (Zhai, 2004). In this dissertation, we first prepared fundamental knowledge of the CMOS technology as well as SRAM. According to the current researches on SRAM (Chang, 2005) (Chen, 2010), we proposed a novel 6t SRAM design which operates in near threshold region to optimize leakage power and speed. Negative word line is introduced to reduce the leakage current. A novel Latch-type voltage sense amplifier is proposed to improve the read speed of the proposed SRAM cell. The proposed SRAM design is implemented in 45nm technology and achieves more than 50% for power reduction, 68% for leakage reduction, 90% for write delay reduction and 78% for read delay reduction compared to traditional 6T SRAM in near threshold region. Although the proposed 6T SRAM inherit the disadvantage of 4T schematic in data retention, the operation stability is still respectable. M.S. in Electrical Engineering, May 2011 Show less
