HIGH PERFORMANCE, HIGH STABILITY AND LOW POWER SRAM DESIGN BY USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS

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Description

As the feature size of silicon semiconductor devices scales down to nanometer range, planar bulk CMOS design and fabrication encounter significant challenges. This situation is exacerbated when it comes to SRAM, as SRAM takes a large part of power consumption and area overhead in modern VLSI... Show moreAs the feature size of silicon semiconductor devices scales down to nanometer range, planar bulk CMOS design and fabrication encounter significant challenges. This situation is exacerbated when it comes to SRAM, as SRAM takes a large part of power consumption and area overhead in modern VLSI processor designs. To achieve higher performance, stability and lower power consumption, carbon nanotube (CNT) has been introduced to SRAM design as an alternative material. The semiconducting single-walled CNTs are promising candidates for the channel material of CMOS devices because of two advantages over the other semiconductor materials: high ON current, leading to high speed and low OFF current, leading to less leakage power. In this research work, characterizing work of technology parameters for 6T carbon nanotube field effect transistor (CNFET) SRAM cell is performed for basic understanding of the relationship between SRAM delay/power and CNFET technology parameters. Stability issue is studied by investigating the diameter and transistor ratio impacts on the SRAM static noise margin (SNM). A stability-optimized 6T CNFET SRAM cell achieves 38.88% reading delay reduction, 21.61% writing delay reduction, 85.65% reading power reduction, 5.88% writing power reduction, 97.80% leakage power reduction, 41.41% SNM increment, 91.23% reading power-delay product (PDP) reduction and 26.23% writing PDP reduction, compared with conventional silicon MOSFET SRAM cell. To mitigate major CNT imperfection impacts on CNFET circuits, a misalignment immune SRAM design method is proposed to eliminate CNT misalignment problem by using etching region defined in circuit layout; and a diameter variation sensing and compensating system is designed to mitigate the negative impacts of CNT diameter variation on SRAM delay and power consumption. A hybrid silicon/CNT 4T SRAM cell design is proposed for low-power high-density cache application, which is better than conventionally used 6T SRAM in terms of power consumption and circuit area. Finally, a design flow of high performance, high stability and low power SRAM is summarized.
Ph.D. in Electrical Engineering, July 2012 Show less

Details
Department

ECE / Electrical and Computer Engineering

Title

HIGH PERFORMANCE, HIGH STABILITY AND LOW POWER SRAM DESIGN BY USING CARBON NANOTUBE FIELD EFFECT TRANSISTORS

Institution

Illinois Institute of Technology

Creator(s)

Wang, Wei

Advisor(s)

Saniie, Jafar

Date

2012-07-07
2012-07

Description

As the feature size of silicon semiconductor devices scales down to nanometer range, planar bulk CMOS design and fabrication encounter significant challenges. This situation is exacerbated when it... Show moreAs the feature size of silicon semiconductor devices scales down to nanometer range, planar bulk CMOS design and fabrication encounter significant challenges. This situation is exacerbated when it comes to SRAM, as SRAM takes a large part of power consumption and area overhead in modern VLSI processor designs. To achieve higher performance, stability and lower power consumption, carbon nanotube (CNT) has been introduced to SRAM design as an alternative material. The semiconducting single-walled CNTs are promising candidates for the channel material of CMOS devices because of two advantages over the other semiconductor materials: high ON current, leading to high speed and low OFF current, leading to less leakage power. In this research work, characterizing work of technology parameters for 6T carbon nanotube field effect transistor (CNFET) SRAM cell is performed for basic understanding of the relationship between SRAM delay/power and CNFET technology parameters. Stability issue is studied by investigating the diameter and transistor ratio impacts on the SRAM static noise margin (SNM). A stability-optimized 6T CNFET SRAM cell achieves 38.88% reading delay reduction, 21.61% writing delay reduction, 85.65% reading power reduction, 5.88% writing power reduction, 97.80% leakage power reduction, 41.41% SNM increment, 91.23% reading power-delay product (PDP) reduction and 26.23% writing PDP reduction, compared with conventional silicon MOSFET SRAM cell. To mitigate major CNT imperfection impacts on CNFET circuits, a misalignment immune SRAM design method is proposed to eliminate CNT misalignment problem by using etching region defined in circuit layout; and a diameter variation sensing and compensating system is designed to mitigate the negative impacts of CNT diameter variation on SRAM delay and power consumption. A hybrid silicon/CNT 4T SRAM cell design is proposed for low-power high-density cache application, which is better than conventionally used 6T SRAM in terms of power consumption and circuit area. Finally, a design flow of high performance, high stability and low power SRAM is summarized. Show less

Type

Dissertation

File type

application/pdf

Access

Restricted Access

Rights

In Copyright
http://rightsstatements.org/page/InC/1.0/

Identifier

http://hdl.handle.net/10560/2941

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