creator Luo, Tianchen advisor Wang, Jia Retiming is a powerful optimization technique for synchronize sequential circuits that relocates delay unit without changing the circuit’s input-output functionality. Wire delay is significant and can no longer be ignored in deep sub-micrometer technologies. Existing algorithms solve the problem of min-area and min-period either optimal or heuristically without taking wire delay into consideration. However, those techniques cannot be applied directly to circuit with wire delay. Recent work solved the min-period problem under wire delay model. This paper proposes an algorithm that solves the problem of min-area wire retiming under fixed clock period optimally and efficiently. Submitted by Dana Lamparello (dlampare@iit.edu) on 2012-02-29T16:20:23Z No. of bitstreams: 1 Tianchen_Luo_THESIS.pdf: 988522 bytes, checksum: 26d7d1eb4edc81d0c0924d8cb9ee4343 (MD5) Made available in DSpace on 2012-02-29T16:20:23Z (GMT). No. of bitstreams: 1 Tianchen_Luo_THESIS.pdf: 988522 bytes, checksum: 26d7d1eb4edc81d0c0924d8cb9ee4343 (MD5) Previous issue date: 2011-05 M.S. in Electrical and Computer Engineering, May 2011 2011-05-09 2011-05 http://hdl.handle.net/10560/2522 en retiming circuit modeling interconnection synthesis circuit optimization Thesis born digital application/pdf In Copyright http://rightsstatements.org/page/InC/1.0/ Restricted Access ECE / Electrical and Computer Engineering Illinois Institute of Technology Affiliated department