creator Zhang, Yunlong advisor Choi, Ken In this thesis, we introduce hash encryption functions which are widely used in a number of protocols as digital signature to protect privacy information. Since the hash algorithm can be speeded up and be more security by physical protection, hash function hardware implementation is more desired today for evaluating its performance and processing data with dramatically increased size. Then we consider those two problems in the hash function hardware implementation: throughput and power consumption. High level of throughput is significant for the efficiency of hash algorithm. By using unfolding transformation, the throughput of hash function can be increased apparently. However, power consumption, area and critical path delay will also be increased. Pipeline and parallelism is an effective technique to decrease the critical path delay, by analyzing the construction of computing process. Another Problem is power consumption which will influence the reliability and cost of device. Clock gating is a widely used and efficiency technique for dynamic power reducing at register transfer level (RTL). There are two basic modes for single level clock gating: XOR-based clock gating and load-enable based clock gating [13]. The former one is based on the comparing between output and input of flip-flops (FFs). Although this XOR-based clock gating technique is not used in our hash function hardware implementation, we will briefly introduce some techniques of this method which is our previous research work for dynamic power reduction by comparing some RTL low power techniques. x Next, load-enable based clock gating which works with an enable signal is introduced. According to the idle mode of some components in our simply hash encryption system, we use this load-enable based clock gating to eliminate wasted toggle rate of some signals, thus reducing dynamic power consumption. Finally, according to the source of dynamic power dissipation, reducing clock frequency is another choice. Frequency trade-off technique is proposed, which combines unrolling transformation with frequency scaling. In this technique, a scope of frequency value is given in each hash function with different number of iteration rounds for trading off low dynamic power consumption and high throughput. Submitted by Liana Khananashvili (khananashvili@iit.edu) on 2013-10-22T17:45:59Z No. of bitstreams: 1 Thesis_signed.pdf: 3707565 bytes, checksum: 5336ee4f0e1c12e5febfc274253c0cb0 (MD5) Made available in DSpace on 2013-10-22T17:45:59Z (GMT). No. of bitstreams: 1 Thesis_signed.pdf: 3707565 bytes, checksum: 5336ee4f0e1c12e5febfc274253c0cb0 (MD5) Previous issue date: 2013-05 M.S. in Electrical Engineering, May 2013 2013-04-30 2013-05 http://hdl.handle.net/10560/3106 en Thesis born digital application/pdf In Copyright http://rightsstatements.org/page/InC/1.0/ Restricted Access ECE / Electrical and Computer Engineering Illinois Institute of Technology Affiliated department