<?xml version='1.0' encoding='utf-8'?>
<mods xmlns="http://www.loc.gov/mods/v3" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" version="3.7" xsi:schemaLocation="http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-7.xsd">
  <titleInfo>
    <title>HIGH PERFORMANCE LOGIC DESIGN FOR ADAPTIVE FIR FETAL ECG ESTIMATION</title>
  </titleInfo>
  <name>
    <role>
      <roleTerm type="text" authority="marcrelator" authorityURI="http://id.loc.gov/vocabulary/relators" valueURI="http://id.loc.gov/vocabulary/relators/cre">creator</roleTerm>
    </role>
    <namePart>Wang, Sizhou</namePart>
  </name>
  <name authority="wikidata" authorityURI="https://www.wikidata.org" valueURI="https://www.wikidata.org/wiki/Q102339844">
    <role>
      <roleTerm type="text" authority="marcrelator" authorityURI="http://id.loc.gov/vocabulary/relators" valueURI="http://id.loc.gov/vocabulary/relators/ths">advisor</roleTerm>
    </role>
    <namePart>Saniie, Jafar</namePart>
  </name>
  <abstract>This thesis presents realizations of IEEE-754 single precision floating point non-invasive fetal ECG estimation based on QR Decomposition Recursive Least Square algorithm (QRD-RLS). Experiments of the system, which is implemented on Xilinx Zynq SoC platform, are carried out with electrocardiogram (ECG) data and the results with analysis are presented. The embedded system design aims for saving resources, streaming pipeline performance and software-aid computation and integration. The challenge of exploiting the system full potential with pseudo-parallel computation on multiple fetal ECG data packets is also examined.</abstract>
  <note type="provenance">Submitted by Liana Khananashvili (khananashvili@iit.edu) on 2014-10-27T18:19:34Z No. of bitstreams: 1 Sizhou_Wang_A20249772_MS_Thesis_May2014.pdf: 1543193 bytes, checksum: 3ec92b817cf3bb49a1656821cf729bcb (MD5)</note>
  <note type="provenance">Made available in DSpace on 2014-10-27T18:19:34Z (GMT). No. of bitstreams: 1 Sizhou_Wang_A20249772_MS_Thesis_May2014.pdf: 1543193 bytes, checksum: 3ec92b817cf3bb49a1656821cf729bcb (MD5) Previous issue date: 2014-05</note>
  <note type="thesis">M.S. in Computer and Electrical Engineering, May 2014</note>
  <originInfo>
    <dateCaptured>2014</dateCaptured>
  </originInfo>
  <originInfo>
    <dateCreated keyDate="yes">2014-05</dateCreated>
  </originInfo>
  <identifier type="hdl">http://hdl.handle.net/10560/3318</identifier>
  <language>
    <languageTerm type="code" authority="rfc3066">en</languageTerm>
  </language>
  <typeOfResource authority="coar" valueURI="http://purl.org/coar/resource_type/c_46ec">Thesis</typeOfResource>
  <physicalDescription>
    <digitalOrigin>born digital</digitalOrigin>
    <internetMediaType>application/pdf</internetMediaType>
  </physicalDescription>
  <accessCondition type="useAndReproduction" displayLabel="rightsstatements.org">In Copyright</accessCondition>
  <accessCondition type="useAndReproduction" displayLabel="rightsstatements.orgURI">http://rightsstatements.org/page/InC/1.0/</accessCondition>
  <accessCondition type="restrictionOnAccess">Restricted Access</accessCondition>
  <name type="corporate">
    <namePart>ECE / Electrical and Computer Engineering</namePart>
    <affiliation>Illinois Institute of Technology</affiliation>
    <role>
      <roleTerm type="text">Affiliated department</roleTerm>
    </role>
  </name>
</mods>