creator Kim, Youngbae advisor Choi, Ken In deep sub-micron technology, leakage power consumption has become a major concern in VLSI circuits, especially for SRAM, which is used to build the cache in System-on-Chip (SOC). In this paper, a low power 8-T SRAM cell, based on carbon nanotube field effect transistor (CNFET), is proposed to circumvent the leakage power issue. Experiment datas show that the proposed SRAM cell can save 97.94% static power consumption compared to existing 6T CNFET SRAM cell. In case of writing, the proposed SRAM cell consumes 39.27% less power than the traditional SRAM cell for writing 0 and 58.79% less for writing 1. Also, because of the adoption of a colaborated voltage sense amplifier and independent read component, our 8T SRAM shows much improved delay performance, the delay is observed to reduce by approximate 30% in write operation and approximate 90% in read operation. Submitted by Erma Thomas (thomase@iit.edu) on 2016-07-20T21:40:23Z No. of bitstreams: 1 etdadmin_upload_427800.zip: 782121 bytes, checksum: a8983c9693e016552871e8c91ea411c3 (MD5) Made available in DSpace on 2016-07-20T21:40:23Z (GMT). No. of bitstreams: 1 etdadmin_upload_427800.zip: 782121 bytes, checksum: a8983c9693e016552871e8c91ea411c3 (MD5) Previous issue date: 2016-05 M.S. in Electrical Engineering, May 2016 2016 2016-05 http://hdl.handle.net/10560/3897 en 8-T SRAM carbon nanotube filed effect transistor low power SRAM SRAM Thesis born digital application/pdf In Copyright http://rightsstatements.org/page/InC/1.0/ Restricted Access ECE / Electrical and Computer Engineering Illinois Institute of Technology Affiliated department