With the rapidly increasing number of elements integrated on a single chip. The area on a chip became much costlier. And the difficulty of planning all the elements has been growing. So, decreasing... Show moreWith the rapidly increasing number of elements integrated on a single chip. The area on a chip became much costlier. And the difficulty of planning all the elements has been growing. So, decreasing the area cost of each single element became important to be considered. In the conventional technology, to cancel the imaginary part of the input impedance, inductors were used in the design of a LNA. However, inductor is an area consuming element, it would cost most of the chip area. To reduce the area cost of LNA, it is important to reduce the number of inductor, the best case is to design a LNA without any inductor. What’s more, without inductor, LNA would be able to work in a wideband frequency, but not a specific narrow-band frequency. But considering the imaginary part of input impedance, the highest frequency would reduce, depending on the f T of the MOSFET used in the design. In this thesis, the design considerations of heterodyne transceiver, which is the most popular architecture in modern RF design, are introduced firstly. Then, to reduce the undesired effect from image signal, a special architecture, called image-ejection architecture, is explained. To implement the proposal function, different architectures are shown. In RF receiver design, Low Noise Amplifier is one of the most important stages in the RX chain. To design a LNA which can meet different requirements of the RX design. Different topologies are explained, including CS stage, CG stage and differential LNA. Besides conventional technique, some up-to-date techniques are also shown, such as modified CG stage. The main propose of this thesis is to design an inductorless LNA. In this LNA design, Noise Canceling technology and Amplifier Enhancement technology were utilized to improve the noise and amplifying performance. After explaining the technologies theoretically, the circuit is simulated in a 65nm technology with working frequency band from 2 to 6 GHz. By the simulation, the gain of the design is beyond 14dB in the whole band, while the noise figure less than 2.8dB. Show less