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  <titleInfo>
    <title>RECONFIGURABLE SYSTEM-ON.CHIP SOLUTION FOR ULTRASONIC IMAGING APPLICATIONS</title>
  </titleInfo>
  <name>
    <role>
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    <namePart>Gal, Paul</namePart>
  </name>
  <name authority="wikidata" authorityURI="https://www.wikidata.org" valueURI="https://www.wikidata.org/wiki/Q102339844">
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      <roleTerm type="text" authority="marcrelator" authorityURI="http://id.loc.gov/vocabulary/relators" valueURI="http://id.loc.gov/vocabulary/relators/ths">advisor</roleTerm>
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    <namePart>Saniie, Jafar</namePart>
  </name>
  <abstract>Ultrasonic system have evolved from a basic single transducer system to full arrays capable of 3-dimensional scans. These advanced systems are design for specific applications and target materials. These systems need to be able to process the vast amount of data that is generated while maintaining portability a flexible and reconfigurable system. Specific hardware accelerators are built to perform ultrasonic signal processing quickly and efficiently. This system allows for a variety of parameters like signal lengths and processing characteristics to be reconfigurable to allow for flexibility for different applications. A system is developed to provide an effective storage and data transfer system which will allows researchers to quickly gather data. Specific compression and reconstruction algorithms are implemented as accelerators to increase the systems overall performance. For data transfer a simple Real Time Operating System and Ethernet connective is developed. This is all implemented on the ZEDBoard Zynq SoC for maximum flexibility and performance.Ultrasonic system have evolved from a basic single transducer system to full arrays capable of 3-dimensional scans. These advanced systems are design for specific applications and target materials. These systems need to be able to process the vast amount of data that is generated while maintaining portability a flexible and reconfigurable system. Specific hardware accelerators are built to perform ultrasonic signal processing quickly and efficiently. This system allows for a variety of parameters like signal lengths and processing characteristics to be reconfigurable to allow for flexibility for different applications. A system is developed to provide an effective storage and data transfer system which will allows researchers to quickly gather data. Specific compression and reconstruction algorithms are implemented as accelerators to increase the systems overall performance. For data transfer a simple Real Time Operating System and Ethernet connective is developed. This is all implemented on the ZEDBoard Zynq SoC for maximum flexibility and performance.Ultrasonic system have evolved from a basic single transducer system to full arrays capable of 3-dimensional scans. These advanced systems are design for specific applications and target materials. These systems need to be able to process the vast amount of data that is generated while maintaining portability a flexible and reconfigurable system. Specific hardware accelerators are built to perform ultrasonic signal processing quickly and efficiently. This system allows for a variety of parameters like signal lengths and processing characteristics to be reconfigurable to allow for flexibility for different applications. A system is developed to provide an effective storage and data transfer system which will allows researchers to quickly gather data. Specific compression and reconstruction algorithms are implemented as accelerators to increase the systems overall performance. For data transfer a simple Real Time Operating System and Ethernet connective is developed. This is all implemented on the ZEDBoard Zynq SoC for maximum flexibility and performance.</abstract>
  <note type="provenance">Submitted by Erma Thomas (thomase@iit.edu) on 2016-04-04T18:09:32Z No. of bitstreams: 1 etdadmin_upload_398440.zip: 2107067 bytes, checksum: 92acf34b13e7f9a9acc06f301cb57420 (MD5)</note>
  <note type="provenance">Made available in DSpace on 2016-04-04T18:09:32Z (GMT). No. of bitstreams: 1 etdadmin_upload_398440.zip: 2107067 bytes, checksum: 92acf34b13e7f9a9acc06f301cb57420 (MD5) Previous issue date: 2015-12</note>
  <note type="thesis">M.S. in Electrical Engineering, December 2015</note>
  <originInfo>
    <dateCaptured>2015</dateCaptured>
  </originInfo>
  <originInfo>
    <dateCreated keyDate="yes">2015-12</dateCreated>
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  <identifier type="hdl">http://hdl.handle.net/10560/3797</identifier>
  <language>
    <languageTerm type="code" authority="rfc3066">en</languageTerm>
  </language>
  <subject>
    <topic>Compression</topic>
  </subject>
  <subject>
    <topic>DSP</topic>
  </subject>
  <subject>
    <topic>FPGA</topic>
  </subject>
  <subject>
    <topic>Hardware/Software Codesign</topic>
  </subject>
  <subject>
    <topic>Signal Processing</topic>
  </subject>
  <subject>
    <topic>Ultrasonics</topic>
  </subject>
  <typeOfResource authority="coar" valueURI="http://purl.org/coar/resource_type/c_46ec">Thesis</typeOfResource>
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  <accessCondition type="useAndReproduction" displayLabel="rightsstatements.orgURI">http://rightsstatements.org/page/InC/1.0/</accessCondition>
  <accessCondition type="restrictionOnAccess">Restricted Access</accessCondition>
  <name type="corporate">
    <namePart>ECE / Electrical and Computer Engineering</namePart>
    <affiliation>Illinois Institute of Technology</affiliation>
    <role>
      <roleTerm type="text">Affiliated department</roleTerm>
    </role>
  </name>
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