creator Krishna Kumar, Ashwitha advisor Saniie, Jafar The hardware support for the Decimal Multiplication is gaining importance in commercial applications including banking, accounting, tax calculations, currency conversion and insurance. In this work, we examine the di erent types of number sys- tems that have been used for executing Decimal Multiplication. A unique signed-digit representation is used for reduced logic and latency. Furthermore, partial product ac- cumulation is performed with Svoboda decimal adder, which is e cient. The imple- mentation of the proposed architecture is modeled using VHDL and then synthesized on FPGA. The hardware resources for this architecture are analyzed. This work presents an important case study for FPGA implementation of Decimal Arithmetic architectures such as ALUs. Submitted by Dana Lamparello (dlampare@iit.edu) on 2013-03-04T17:57:43Z No. of bitstreams: 1 Decimal_Multiplication_architecture_for_FPGA_Implementation.pdf: 510405 bytes, checksum: 0af182de612d878316b15788379bcb80 (MD5) Made available in DSpace on 2013-03-04T17:57:43Z (GMT). No. of bitstreams: 1 Decimal_Multiplication_architecture_for_FPGA_Implementation.pdf: 510405 bytes, checksum: 0af182de612d878316b15788379bcb80 (MD5) Previous issue date: 2012-07 M.S. in Electrical Engineering, July 2012 2012-07-23 2012-07 http://hdl.handle.net/10560/2908 en Thesis born digital application/pdf In Copyright http://rightsstatements.org/page/InC/1.0/ Restricted Access ECE / Electrical and Computer Engineering Illinois Institute of Technology Affiliated department