creator Ramani, Arun Ramnath advisor Choi, Ken This dissertation has two new circuit level designs proposed. One a Dual edge triggered Near threshold State Retentive flip flop and another a 9TSRAM cell for operation in Sub-Threshold Region. Since power consumption has become one of the major issues in the Ultra Deep Sub-Micron Technology, we have seen ideas where power saving methods being evolving and these given priority. Scaling the supply voltage into the near-threshold and the sub-thresholdregion for low power operation is possible. Power reduction in memory circuits with a little compromise on performance is very useful as these memory elements are the ones that form a major part of a integrated chip. The first part of this dissertation proposes a new dual edge triggered near threshold state-retentive pulsed latch or flip flop for low-power applications. The proposed circuit uses the idea of power gating during the sleep or idle mode thereby avoiding leakage but still retaining its state. It uses a dual edge triggered pulse which triggers the circuit at both the rising and falling edges of the clock. The circuit used low Vth Devices only and hence can operate at a Vdd as low as 0.5 V. The circuit was simulated using HSPICE at 45nm technology. In the second part of this dissertation, operation of various SRAM designs in sub-threshold region is examined and the ones which overcome the challenges that arise from operating in the sub-threshold region are also explained. Among the chosen designs for performance evaluation, the successful designs were the ones which resulted in proper read and write at sub-threshold supply voltage. Best combinations of them were taken and along with the considerations with respect to read noise margin, were made into a new SRAM design operating in subthreshold region. The circuit was simulated using HSPICE at 45nm technology using Predictive Technology Models. Submitted by Lance Garrison (garrlanc@my.dom.edu) on 2012-02-20T19:44:57Z No. of bitstreams: 2 Arun_Ramnath_Ramani_Thesis.pdf: 857206 bytes, checksum: b42a4fdb80d74f174ef7aafc63531fe2 (MD5) Front_Page.pdf: 87699 bytes, checksum: f583c012bbd07de13d77f5d2700d1706 (MD5) Made available in DSpace on 2012-02-20T19:44:57Z (GMT). No. of bitstreams: 2 Arun_Ramnath_Ramani_Thesis.pdf: 857206 bytes, checksum: b42a4fdb80d74f174ef7aafc63531fe2 (MD5) Front_Page.pdf: 87699 bytes, checksum: f583c012bbd07de13d77f5d2700d1706 (MD5) Previous issue date: 2011-07 M.S. in Electrical Engineering, July 2011 2011-07 2011-07 http://hdl.handle.net/10560/2474 en Thesis born digital application/pdf In Copyright http://rightsstatements.org/page/InC/1.0/ Restricted Access ECE / Electrical and Computer Engineering Illinois Institute of Technology Affiliated department