
<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
  <dc:title>A NEAR-THRESHOLD FLIP FLOP AND A SUB-THRESHOLD SRAM FOR LOW-POWER APPLICATIONS</dc:title>
  <dc:creator>Ramani, Arun Ramnath</dc:creator>
  <dc:description>This dissertation has two new circuit level designs proposed. One a Dual edge triggered Near threshold State Retentive flip flop and another a 9TSRAM cell for operation in Sub-Threshold Region. Since power consumption has become one of the major issues in the Ultra Deep Sub-Micron Technology, we have seen ideas where power saving methods being evolving and these given priority. Scaling the supply voltage into the near-threshold and the sub-thresholdregion for low power operation is possible. Power reduction in memory circuits with a little compromise on performance is very useful as these memory elements are the ones that form a major part of a integrated chip. The first part of this dissertation proposes a new dual edge triggered near threshold state-retentive pulsed latch or flip flop for low-power applications. The proposed circuit uses the idea of power gating during the sleep or idle mode thereby avoiding leakage but still retaining its state. It uses a dual edge triggered pulse which triggers the circuit at both the rising and falling edges of the clock. The circuit used low Vth Devices only and hence can operate at a Vdd as low as 0.5 V. The circuit was simulated using HSPICE at 45nm technology. In the second part of this dissertation, operation of various SRAM designs in sub-threshold region is examined and the ones which overcome the challenges that arise from operating in the sub-threshold region are also explained. Among the chosen designs for performance evaluation, the successful designs were the ones which resulted in proper read and write at sub-threshold supply voltage. Best combinations of them were taken and along with the considerations with respect to read noise margin, were made into a new SRAM design operating in subthreshold region. The circuit was simulated using HSPICE at 45nm technology using Predictive Technology Models.</dc:description>
  <dc:description>M.S. in Electrical Engineering, July 2011</dc:description>
  <dc:contributor>Choi, Ken</dc:contributor>
  <dc:date>2011-07</dc:date>
  <dc:date>2011-07</dc:date>
  <dc:type>Thesis</dc:type>
  <dc:format>application/pdf</dc:format>
  <dc:identifier>islandora:6516</dc:identifier>
  <dc:identifier>http://hdl.handle.net/10560/2474</dc:identifier>
  <dc:source>ECE / Electrical and Computer Engineering</dc:source>
  <dc:source>Illinois Institute of Technology</dc:source>
  <dc:language>en</dc:language>
  <dc:rights>In Copyright</dc:rights>
  <dc:rights>http://rightsstatements.org/page/InC/1.0/</dc:rights>
  <dc:rights>Restricted Access</dc:rights>
</oai_dc:dc>
