A NEAR-THRESHOLD FLIP FLOP AND A SUB-THRESHOLD SRAM FOR LOW-POWER APPLICATIONS
RAMANI, ARUN RAMNATH
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This dissertation has two new circuit level designs proposed. One a Dual edge triggered Near threshold State Retentive flip flop and another a 9TSRAM cell for operation in Sub-Threshold Region. Since power consumption has become one of the major issues in the Ultra Deep Sub-Micron Technology, we have seen ideas where power saving methods being evolving and these given priority. Scaling the supply voltage into the near-threshold and the sub-thresholdregion for low power operation is possible. Power reduction in memory circuits with a little compromise on performance is very useful as these memory elements are the ones that form a major part of a integrated chip. The first part of this dissertation proposes a new dual edge triggered near threshold state-retentive pulsed latch or flip flop for low-power applications. The proposed circuit uses the idea of power gating during the sleep or idle mode thereby avoiding leakage but still retaining its state. It uses a dual edge triggered pulse which triggers the circuit at both the rising and falling edges of the clock. The circuit used low Vth Devices only and hence can operate at a Vdd as low as 0.5 V. The circuit was simulated using HSPICE at 45nm technology. In the second part of this dissertation, operation of various SRAM designs in sub-threshold region is examined and the ones which overcome the challenges that arise from operating in the sub-threshold region are also explained. Among the chosen designs for performance evaluation, the successful designs were the ones which resulted in proper read and write at sub-threshold supply voltage. Best combinations of them were taken and along with the considerations with respect to read noise margin, were made into a new SRAM design operating in subthreshold region. The circuit was simulated using HSPICE at 45nm technology using Predictive Technology Models.